Showing posts with label efficient. Show all posts
Showing posts with label efficient. Show all posts

Wednesday, 8 February 2017

efficient channel model evaluating NoC architectures DOI: 10.1109/SBAC-PADW.2016.23

Opoku Agyeman, M., Vien, Q.-T., Hill, G., Turner, S. J. and Mak, T. (2017) An efficient channel model for evaluating Wireless NoC architectures. In: 2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW). Online: IEEE. 978-1-5090-4844-1. pp. 85-90.

DOI: 10.1109/SBAC-PADW.2016.23

Abstact
Wireless Networks-on-Chip (WiNoCs) have emerged to solve the scalability and performance bottleneck of conventional wired NoC architectures. However unlike communication in the macro-world, on-chip communication poses several constraints, hence there is the need for simulation and design tools that consider the effect of the wireless channel at the nanotechnology level. In this paper, we present a parameterizable channel model for WiNoCs which takes into account practical issues and constraints of the propagation medium, such as transmission frequency, operating temperature, ambient pressure and distance between the on-chip antennas. The proposed channel model demonstrates that total path loss of the wireless channel in WiNoCs suffers from not only dielectric propagation loss (DPL) but also molecular absorption attenuation (MAA) which reduces the reliability of the system.



All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

Tuesday, 8 November 2016

efficient 2D router architecture to extend 3D NoC-based multi-core architecture performance

Opoku Agyeman, M. and Zong, W. (2016) An efficient 2D router architecture for extending the performance of inhomogeneous 3D NoC-based multi-core architectures. In: SBAC-PAD Workshop on Applications for Multi-Core Architectures. USA: IEEE . 

Abstract
To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-on-Chip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs.

To read more go http://nectar.northampton.ac.uk/8918/ or http://www.cos.ufrj.br/wamca/program.php

All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

Wednesday, 19 October 2016

An efficient channel model for evaluating Wireless NoC architectures

An efficient channel model for evaluating Wireless NoC architectures
Opoku Agyeman, M., Vien, Q.-T., Hill, G., Turner, S. J. and Mak, T. 
Workshop on Applications for Multi-Core Architectures.  
7th Workshop on Applications for Multi-Core Architectures (WAMCA) 


Abstract
Wireless Networks-on-Chip (WiNoCs) have emerged to solve the scalability and performance bottleneck of conventional wired NoC architectures. However unlike communication in the macro-world, on-chip communication poses several constraints, hence there is the need for simulation and design tools that consider the effect of the wireless channel at the nanotechnology level. In this paper, we present a parameterizable channel model for WiNoCs which takes into account practical issues and constraints of the propagation medium, such as transmission frequency, operating temperature, ambient pressure and distance between the on-chip antennas. The proposed channel model demonstrates that total path loss of the wireless channel in WiNoCs suffers from not only dielectric propagation loss (DPL) but also molecular absorption attenuation (MAA) which reduces the reliability of the system


All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon