efficient 2D router architecture to extend 3D NoC-based multi-core architecture performance

Opoku Agyeman, M. and Zong, W. (2016) An efficient 2D router architecture for extending the performance of inhomogeneous 3D NoC-based multi-core architectures. In: SBAC-PAD Workshop on Applications for Multi-Core Architectures. USA: IEEE . 

Abstract
To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-on-Chip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs.

To read more go http://nectar.northampton.ac.uk/8918/ or http://www.cos.ufrj.br/wamca/program.php

All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

Michael wins best in track at the Euromicro DSD/SEAA 2016 conference

A recently presented by Dr Michael Opoku-Agyeman was award best in track at the Euromicro DSD/SEAA 2016 conference .


Zong, W., Wang, L., Xu, Q. and Opoku Agyeman, M. (2016) SlideAcross: a low-latency adaptive router for chip multi-processor.In: Proceedings of Euromicro DSD/SEAA 2016. Cyprus: IEEE.

Abstract
The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. This router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low loads. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a nonspeculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications’ execution time by 16.9% in average compared to low-latency router SWIFT

To read more go to SlideAcross: a low-latency adaptive router for chip multi-processor. 




All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon