Adaptive virtual MIMO single cluster optimization in a small cell

Kanakis, T., Opoku Agyeman, M. and Bakaoukas, A. (2016) Adaptive virtual MIMO single cluster optimization in a small cell.Paper presented to: 7th International Conference on Cloud Computing, Data Science & Engineering, Amity University, Noida, India, 12-13 January 2017. (Accepted)

Abstract

Adaptive Virtual MIMO optimized in a single cluster of small cells is shown in this paper to achieve near Shannon
channel capacity when operating with partial or no Channel State Information. Although, access links have enormously increased in the recent years, the operational system complexity remains linear regardless of the number of access nodes in the system proposed.

Adaptive Virtual MIMO optimized in a single cluster performs a theoretical information spectral efficiency, almost equal to that of the upper bounds of a typical mesh network, up to 43 bits/s/Hz at a SNR of 30dB while the BER performance remains impressively low hitting the 10−6 at an SNR of about 13 dB when the theoretical upper bound of an ideal small cell mesh network achieves the 10−6 at a SNR of 12.5 dB. In addition, in a sub-optimum channel condition, the channel capacity and BER performance of the proposed solution is shown to drastically delay saturation even for the very high SNR.

All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

Michael wins best in track at the Euromicro DSD/SEAA 2016 conference

A recently presented by Dr Michael Opoku-Agyeman was award best in track at the Euromicro DSD/SEAA 2016 conference .


Zong, W., Wang, L., Xu, Q. and Opoku Agyeman, M. (2016) SlideAcross: a low-latency adaptive router for chip multi-processor.In: Proceedings of Euromicro DSD/SEAA 2016. Cyprus: IEEE.

Abstract
The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. This router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low loads. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a nonspeculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications’ execution time by 16.9% in average compared to low-latency router SWIFT

To read more go to SlideAcross: a low-latency adaptive router for chip multi-processor. 




All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

SlideAcross: novel distributing method for on chip multi-processor data

Zong, W., Wang, L., Xu, Q. and Opoku Agyeman, M. (2016) SlideAcross: a low-latency adaptive router for chip multi-processor.In: Proceedings of Euromicro DSD/SEAA 2016. Cyprus: IEEE. (Accepted)

Abstract
The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. This router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low loads. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a nonspeculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications’ execution time by 16.9% in average compared to low-latency router SWIFT

To read more go to SlideAcross: a low-latency adaptive router for chip multi-processor. 

If you'd like to find out more about Computing at the University of Northampton go to: www.computing.northampton.ac.uk. All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with