efficient channel model evaluating NoC architectures DOI: 10.1109/SBAC-PADW.2016.23

Opoku Agyeman, M., Vien, Q.-T., Hill, G., Turner, S. J. and Mak, T. (2017) An efficient channel model for evaluating Wireless NoC architectures. In: 2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW). Online: IEEE. 978-1-5090-4844-1. pp. 85-90.

DOI: 10.1109/SBAC-PADW.2016.23

Abstact

Wireless Networks-on-Chip (WiNoCs) have emerged to solve the scalability and performance bottleneck of conventional wired NoC architectures. However unlike communication in the macro-world, on-chip communication poses several constraints, hence there is the need for simulation and design tools that consider the effect of the wireless channel at the nanotechnology level. In this paper, we present a parameterizable channel model for WiNoCs which takes into account practical issues and constraints of the propagation medium, such as transmission frequency, operating temperature, ambient pressure and distance between the on-chip antennas. The proposed channel model demonstrates that total path loss of the wireless channel in WiNoCs suffers from not only dielectric propagation loss (DPL) but also molecular absorption attenuation (MAA) which reduces the reliability of the system.

To read the full-text go to either An efficient channel model for evaluating Wireless NoC architectures or http://ieeexplore.ieee.org/document/7803701/

All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

Adaptive virtual MIMO single cluster optimization in a small cell

Kanakis, T., Opoku Agyeman, M. and Bakaoukas, A. (2016) Adaptive virtual MIMO single cluster optimization in a small cell.Paper presented to: 7th International Conference on Cloud Computing, Data Science & Engineering, Amity University, Noida, India, 12-13 January 2017. (Accepted)

Abstract

Adaptive Virtual MIMO optimized in a single cluster of small cells is shown in this paper to achieve near Shannon
channel capacity when operating with partial or no Channel State Information. Although, access links have enormously increased in the recent years, the operational system complexity remains linear regardless of the number of access nodes in the system proposed.

Adaptive Virtual MIMO optimized in a single cluster performs a theoretical information spectral efficiency, almost equal to that of the upper bounds of a typical mesh network, up to 43 bits/s/Hz at a SNR of 30dB while the BER performance remains impressively low hitting the 10−6 at an SNR of about 13 dB when the theoretical upper bound of an ideal small cell mesh network achieves the 10−6 at a SNR of 12.5 dB. In addition, in a sub-optimum channel condition, the channel capacity and BER performance of the proposed solution is shown to drastically delay saturation even for the very high SNR.

All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

Design of performance-aware resilient wireless NoC architectures

Opoku Agyeman, M., Wen, Z., Kanakis, T., Tong, K.-F. and Mak, T. (2016) Towards the practical design of performance-aware resilient wireless NoC architectures. In: 7th International Conference on Cloud Computing, Data Science & Engineering. USA: IEEE. 


Abstract
Recently, an improved surface wave-enabled communication fabric has been proposed to solve the reliability issues of emerging hybrid wired-wireless Network-on-Chip (WiNoC) architectures. Thus, providing a promising solution to the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing on future System-on-Chip (SoC) design. However, WiNoCs trade-off optimized performance for cost by restricting the number of area and power hungry wireless nodes. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow wired routers in such emerging hyhbrid NoCs. The proposed router is able to redistribute traffic in the network to alleviate average packet latency at both low and high traffic conditions. As a second contribution the paper presents an experimental evaluation of a practically implemented surface wave communication fabric. By reducing the latency between the wired nodes and wireless nodes the proposed router can improve performance efficiency in terms of average packet delay by an average of 50% in WiNoCs.


All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

Michael wins his second award.

Opoku Agyeman, M., Vien, Q.-T. and Mak, T. (2016) 

An analytical channel model for emerging wireless Networks-on-Chip. 

IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2016). 

France: IEEE Computer Society

Abstract
Recently wireless Networks-on-Chip (WiNoCs) have been proposed to overcome the scalability and performance limitations of traditional multi-hop wired NoC architectures. However, the adaptation of wireless technology for on-chip communication is still in its infancy. Consequently, several challenges such as simulation and design tools that consider the technological constraints imposed by the wireless channel are yet to be addressed. To this end, in this paper, we propose and efficient channel model for WiNoCs which takes into account practical issues and constraints of the propagation medium, such as transmission frequency, operating temperature, ambient pressure and distance between the on-chip antennas. The proposed channel model demonstrates that total path loss of the wireless channel in WiNoCs suffers from not only dielectric propagation loss (DPL) but also molecular absorption attenuation (MAA) which reduces the reliability of the system.

some related posts

• https://computingnorthampton.blogspot.co.uk/2016/11/efficient-2d-router-architecture-to.html
• https://computingnorthampton.blogspot.co.uk/2016/11/a-parameterizable-channel-model-for.html
• https://computingnorthampton.blogspot.co.uk/2016/10/an-efficient-channel-model-for.html
• https://computingnorthampton.blogspot.co.uk/2016/11/social-analysis-of-publications.html

All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

efficient 2D router architecture to extend 3D NoC-based multi-core architecture performance

Opoku Agyeman, M. and Zong, W. (2016) An efficient 2D router architecture for extending the performance of inhomogeneous 3D NoC-based multi-core architectures. In: SBAC-PAD Workshop on Applications for Multi-Core Architectures. USA: IEEE . 

Abstract
To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-on-Chip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs.

To read more go http://nectar.northampton.ac.uk/8918/ or http://www.cos.ufrj.br/wamca/program.php

All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

Michael wins best in track at the Euromicro DSD/SEAA 2016 conference

A recently presented by Dr Michael Opoku-Agyeman was award best in track at the Euromicro DSD/SEAA 2016 conference .


Zong, W., Wang, L., Xu, Q. and Opoku Agyeman, M. (2016) SlideAcross: a low-latency adaptive router for chip multi-processor.In: Proceedings of Euromicro DSD/SEAA 2016. Cyprus: IEEE.

Abstract
The non-uniform distributed traffic of chip multiprocessor (CMP) demands an on-chip communication infrastructure which is able to avoid congestion under high traffic conditions while possessing minimal pipeline delay at low load conditions. In this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to meet the communication needs of CMPs. This router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low loads. When the output port required intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a nonspeculative low-latency pipeline. By combining the low-complexity bypassing technique together with adaptive routing, the proposed router architecture can achieve low-latency communication under various traffic loads. Simulation shows that proposed router can reduce applications’ execution time by 16.9% in average compared to low-latency router SWIFT

To read more go to SlideAcross: a low-latency adaptive router for chip multi-processor. 




All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon