dark-silicon era for many-core architectures

A new paper by Ofori-Attah, E., Wang, X. and Opoku Agyeman, M. (2018) A survey of system level power management schemes in the dark-silicon era for many-core architectures. EAI Endorsed Transactions on Industrial Networks and Intelligent Systems. 5(15) 2410-0218.
https://doi.org/10.4108/eai.19-9-2018.155569

Abstract:
Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with many-core integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

Full paper: 
http://nectar.northampton.ac.uk/10526/1/A%20Survey%20of%20System%20Level%20Power%20Management%20Schemes%20in%20the%20Dark-Silicon%20Era%20for%20Many-Core%20Architectures.pdf




All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

efficient 2D router architecture to extend 3D NoC-based multi-core architecture performance

Opoku Agyeman, M. and Zong, W. (2016) An efficient 2D router architecture for extending the performance of inhomogeneous 3D NoC-based multi-core architectures. In: SBAC-PAD Workshop on Applications for Multi-Core Architectures. USA: IEEE . 

Abstract
To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-on-Chip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs.

To read more go http://nectar.northampton.ac.uk/8918/ or http://www.cos.ufrj.br/wamca/program.php

All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon