dark-silicon era for many-core architectures

A new paper by Ofori-Attah, E., Wang, X. and Opoku Agyeman, M. (2018) A survey of system level power management schemes in the dark-silicon era for many-core architectures. EAI Endorsed Transactions on Industrial Networks and Intelligent Systems. 5(15) 2410-0218.
https://doi.org/10.4108/eai.19-9-2018.155569

Abstract:
Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with many-core integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

Full paper: 
http://nectar.northampton.ac.uk/10526/1/A%20Survey%20of%20System%20Level%20Power%20Management%20Schemes%20in%20the%20Dark-Silicon%20Era%20for%20Many-Core%20Architectures.pdf




All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon

An efficient channel model for evaluating Wireless NoC architectures

An efficient channel model for evaluating Wireless NoC architectures
Opoku Agyeman, M., Vien, Q.-T., Hill, G., Turner, S. J. and Mak, T. 
Workshop on Applications for Multi-Core Architectures.  
7th Workshop on Applications for Multi-Core Architectures (WAMCA) 


Abstract
Wireless Networks-on-Chip (WiNoCs) have emerged to solve the scalability and performance bottleneck of conventional wired NoC architectures. However unlike communication in the macro-world, on-chip communication poses several constraints, hence there is the need for simulation and design tools that consider the effect of the wireless channel at the nanotechnology level. In this paper, we present a parameterizable channel model for WiNoCs which takes into account practical issues and constraints of the propagation medium, such as transmission frequency, operating temperature, ambient pressure and distance between the on-chip antennas. The proposed channel model demonstrates that total path loss of the wireless channel in WiNoCs suffers from not only dielectric propagation loss (DPL) but also molecular absorption attenuation (MAA) which reduces the reliability of the system


All views and opinions are the author's and do not necessarily reflected those of any organisation they are associated with. Twitter: @scottturneruon