- Al Barrak, A., Al-Sherbaz, A., Kanakis, T. and Crockett, R. G. M. (2017) Utilisation of multipath phenomenon to improve the performance of BCH and RS codes. In: 8th Computer Science & Electronic Engineering Conference. New York: IEEE. 978-1-5090-2050-8. pp. 6-11.
In wireless communication, there exists a phenomenon known as ‘multipath’. This phenomenon is considered as a disadvantage because it causes interference. The multipath phenomenon results in an antenna receiving two or more signals from the same sent signal from different paths. This paper considers them as redundant copies of the transmitted data and utilises them to improve the performance of forward error correction (FEC) codes without extra redundancy, in order to improve data transmission reliability and increase the bit rate over wireless communication channels. The system was evaluated in bit error rate (BER) and used Bose, Ray-Chaudhuri and Hocquenghem (BCH) and Reed-Solomon (RS) codes as FEC. The results showed that the utilisation of the multipath improves the performance of FEC. Furthermore, the performance of FEC codes had t1 error correction capability and employed the multipath is better than FEC codes have t2 error correction capability and without the multipath, where t1 < t2. Consequently, the bit rate is increased, and communication reliability is improved without extra redundancy.
- Al-Waisi, Z. and Opoku Agyeman, M. (2017) An overview of on-chip cache coherence protocols. In: IEEE IntelliSys Conference 2017 Proceedings. London: IEEE. (Accepted)
Cache coherence protocols play an important role in the performance of distributed and centralized shared-memory of a multiprocessor, and it they are required for maintaining data consistency in a chip-multiprocessor system (CMP). Thus, cache protocols play a major role in improving the performance of multiprocessor systems. Specifically, an efficient cache coherence protocol should ensure the updating of processor data, broadcasting valid data to all other processors and main memory to prevent the main memory or other processors from loading invalid values. To address this issue of efficiency in maintaining cache coherency, several contribution, such as using Invalidation-based protocols with a write through cache coherence, have been made over the past years. This paper presents an overview of emerging cache coherence protocols which aim at improving the performance of CMPs. Furthermore, an example of using an Invalidation-based protocol with a write through for solving cache’s coherency is provided.
- Opoku Agyeman, M., Vien, Q.-T., Hill, G., Turner, S. J. and Mak, T. (2017) An efficient channel model for evaluating Wireless NoC architectures. In: 2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW). Online: IEEE. 978-1-5090-4844-1. pp. 85-90.
Wireless Networks-on-Chip (WiNoCs) have emerged to solve the scalability and performance bottleneck of conventional wired NoC architectures. However unlike communication in the macro-world, on-chip communication poses several constraints, hence there is the need for simulation and design tools that consider the effect of the wireless channel at the nanotechnology level. In this paper, we present a parameterizable channel model for WiNoCs which takes into account practical issues and constraints of the propagation medium, such as transmission frequency, operating temperature, ambient pressure and distance between the on-chip antennas. The proposed channel model demonstrates that total path loss of the wireless channel in WiNoCs suffers from not only dielectric propagation loss (DPL) but also molecular absorption attenuation (MAA) which reduces the reliability of the system.
- Opoku Agyeman, M. and Zong, W. (2017) An efficient 2D router architecture for extending the performance of inhomogeneous 3D NoC-based multi-core architectures. In: 2016 International Symposium on Computer Architecture and High Performance Computing Workshops (SBAC-PADW). USA: IEEE . 978-1-5090-4844-1. pp. 79-84.
o meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-on-Chip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs.
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